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1 i n development features: +3.3v core power supply +2.5v or +3.3v clock output power supply - independent clock output bank power supplies output frequency range: 6 mhz to 200 mhz output-output skew < 100 ps cycle-cycle jitter < 100 ps 2% maximum output duty cycle eight lvttl outputs with se lectable drive strength selectable positive- or ne gative-edge synchronization selectable phase-locked loop (pll) frequency range and lock indicator phase adjustments in 625 to 1300 ps steps up to 7.8 ns (1-6,8,10,12) x multiply and (1/2,1/4) x divide ratios compatible with spread-s pectrum reference clocks power-down mode selectable reference input divider radiation performance - total-dose tolerance: 100 krad (si) to >1 mrad (si) - sel immune > 109 mev-cm 2 /mg - seu saturated cross section: 1e-8cm 2 /device - seu let onset : 109 mev-cm 2 /mg military temperature range: -55 o c to +125 o c packaging options: - 48-lead ceramic flatpack - 49-pin ceramic cga (pending) standard microcircuit drawing: 5962-05214 - qml-q and qml-v compliant part introduction: the ut7r995 is a low-voltage, lo w-power, eight-output, 6-to- 200 mhz clock driver. it featur es output phase programmabil- ity which is necessary to optimize the timing of high-perfor- mance microprocessor and communication systems. the user programs both the frequency and the phase of the out- put banks through nf[1:0] and ds[1:0] pins. the adjustable phase feature allows the user to skew the outputs to lead or lag the reference clock. connect an y one of the outputs to the feedback input to achieve diff erent reference frequency multi- plication and division ratios. the device also features split output bank power supplies which enable the user to run two banks (1qn and 2qn) at a power supply level different from that of the other 2 banks (3qn and 4qn). the ternary pe/hd pin controls the synchro- nization of output signals to either the rising or the falling edge of the reference clock and select s the drive strength of the out- put buffers. the ut7r995 interf aces to either a digital clock reference or a quartz crystal. the flexible reference interface maximizes the number of refere nce options available to the user. 1234567 a v ss pe/hd 3f1 pd /div 4f1 fs v ss b v ss v dd 3f0 soe 4f0 v dd v ss c3q03q1v dd q3 xtal1 v dd q4 4q1 4q0 d v dd v ss v ss fb v dd v ss v dd e2q02q1v dd q1 xtal2 v dd q1 1q1 1q0 f v ss v dd 2f0 lock 1f0 v dd v ss g v ss ds0 2f1 ds1 1f1 test v ss figure 1a. 49-pin ceramic cga (9mm x 9mm) figure 1b. 48-lead ceramic flatpack pin description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 4f0 4f1 soe pd/div pe/hd v dd v dd q3 3q1 3q0 v ss v ss v dd fb v dd v ss v ss 2q1 2q0 v dd q1 lock v ss ds0 ds1 1f0 3f1 3f0 fs v ss v ss v dd q4 4q1 4q0 v ss v ss v dd xtal1 xtal2 v dd v ss v ss 1q1 1q0 v dd q1 v ss test 2f1 2f0 1f1 ut7r995 standard products ut7r995 radhard clock generator advanced data sheet march 21, 2005
2 i n development pd /div xtal1 3 test 33 3 pll /r pe/hd fs 3 3 /n 3 3 3 3 3 3 3 3 phase select phase select phase select and /k phase select and /m fb ds[1:0] 1f[1:0] 2f[1:0] 3f[1:0] 4f[1:0] lock 1q0 1q1 2q0 2q1 3q0 3q1 4q0 4q1 v ddq3 v ddq4 soe figure 2. ut7r995 block diagram v ddq1 xtal2
3 i n development 1.0 device configuration: the outputs of the ut7r995 can be configured to run at fre- quencies ranging from 6 mhz to 200 mhz. each output bank has the ability to run at separa te frequencies and with various phase skew. depending upon the output used for feedback to the pll, numerous clock division and multiplication options exist. the following discussion and list of tables will summarize the available configuration options for the ut7r995. tables 1 through 11, are relevant to the following configuration discus- sions. table 1. feedback divider settings (n-factor) table 2. reference divider settings (r-factor) table 3. output divider se ttings - bank 3 (k-factor) table 4. output divider se ttings - bank 4 (m-factor) table 5. frequency divider summary table 6. calculating output frequency settings table 7. frequency range select table 8. multiplication factor (mf) calculation table 9. output skew settings table 10: signal propagation delays in various media table 11. pe/hd settings table 12. power supply constraints 1.1 divider configuration settings: the feedback input divider is controlled by the 3-level ds[1:0] pins as indicated in table 1 an d the reference input divider is controlled by the 3-level pd /div pin as indicated in table 2. although the reference divider will continue to operate when the ut7r995 is in the standard test mode of operation, the feedback divider will not be available. note: 1. when pd /div = low, the device enters power-down mode. in addition to the reference and feedback dividers, the ut7r995 includes output dividers on bank 3 and bank 4, which are controlled by 3f[1:0] and 4f[1:0] as indicated in ta- bles 3 and 4, respectively. note: 1. these states are used to program the phase of the respective banks. please see equation 1 along with tables 8 and 9. note: 1. these states are used to program the phase of the respective banks. please see equation 1 along with tables 8 and 9. each of the four divider options and their respective settings are summarized in table 5. by appl ying the divider options in ta- ble 5 to the calculations shown in table 6, the user determines the proper clock frequenc y for every output bank. table 1: feedback divider settings ( n-factor ) ds[1:0] feedback input divider - (n) permitted output divider (k or m) connected to fb ll 2 1 or 2 lm 3 1 lh 4 1, 2, or 4 ml 5 1 or 2 mm 1 1, 2, or 4 mh 6 1 or 2 hl 8 1 or 2 hm 10 1 hh 12 1 table 2: reference divider settings ( r-factor ) pd /div operating mode reference input divider - (r) low 1 powered down not applicable mid normal operation 2 high normal operation 1 table 3: output divider settings - bank 3 ( k-factor ) 3f(1:0) bank 3 output divider - (k) ll 2 hh 4 other 1 1 table 4: output divider settings - bank 4 ( m-factor ) 4f[1:0] bank 4 output divider (m) ll 2 other 1 1 table 5: frequency divider summary division factors available divider settings n 1, 2, 3, 4, 5, 6, 8, 10, 12 r1, 2 k1, 2, 4 m1, 2
4 i n development notes: 1. these outputs are undivided copies of the vco clock. therefore, the formulas in this column can be used to calculate the nom inal vco operating frequency (f nom ) at a given reference frequency (f xtal ) and the divider and feedback configuratio n. the user must select a configuration and a reference frequency that will generate a vco frequency that is within the range specified by fs pin. please see table 7. 1.2 frequency range and skew selection: the pll in the ut7r995 operates within three nominal fre- quency ranges. each of which is selectable by the user through the 3-level fs control pin. the selected fs settings given in ta- ble 7 determine the nominal oper ating frequency range of the divide-by-one outputs of the ut7r995. reference the first col- umn of equation in table 6 to calculate the value of f nom for any given feedback clock. selectable output skew is in discrete increments of time unit (t u ). the value of t u is determined by the fs setting and the maximum nominal frequency. the equation to be used to deter- mine the t u value is as follows: the f nom term, selected by the fs si gnal, is found in table 7, and the multiplication factor (mf), also determined by fs, is shown in table 8. after calculating the time unit (t u ) based on the nominal pll frequency (f nom ) and multiplication fact or (mf), the circuit designer plans routing requirement s of each clock output and its respective destination receiver. w ith an understanding of signal propagation delays through a conductive medium (see table 10), the designer specifies trace lengths which ensure a signal propagation delay that is equal to one of the t u multiples show in table 9. for each output bank, the t u skew factors are select- ed with the tri-level, bank-specific, nf[1:0] pins. table 6: calculating output frequency settings configuration output frequency clock output connected to fb 1q[1:0] 1 and 2q[1:0] 1 3q[1:0] 4q[1:0] 1qn or 2qn (n/r) * f xtal (n/r) * (1/k) * f xtal (n/r) * (1/m) * f xtal 3qn (n/r) * k * f xtal (n/r) * f xtal (n/r) * (k/m) * f xtal 4qn (n/r) * m * f xtal (n/r) * (m/k) * f xtal (n/r) * f xtal table 7: frequency range select fs nominal pll frequency range (f nom ) l 24 to 50 mhz m 48 to 100mhz h 96 to 200 mhz mf) * nom (f 1 u t 1. equation =
5 i n development notes: 1. nf[1:0] = ll disables bank specific outputs if test=mid and soe = high. 2. when test=mid or high, the divide-by-2, divide-by-4, and inversion options function as defined in table 9. 3. when 4q[1:0] are set to run inverted (4f[1:0] = hh), soe disables these out- puts high when pe/hd = high or mid, soe disables them low when pe/hd = low. table 8: mf calculation fs mf f nom at which t u is 1.0ns l 32 31.25 mhz m 16 62.5 mhz h 8 125 mhz table 9: output skew settings nf[1:0] skew 1q[1:0], 2q[1:0] skew 3q[1:0] skew 4q[1:0] ll 1, 2 -4t u divide by 2 divide by 2 lm -3t u -6t u -6t u lh -2t u -4t u -4t u ml -1t u -2t u -2t u mm zero skew zero skew zero skew mh +1t u +2t u +2t u hl +2t u +4t u +4t u hm +3t u +6t u +6t u hh 2 +4t u divide by 4 inverted 3 table 10: examples of common signal propagation delays found in various mediums medium propagation delay (ps/inch) dielectric constant air (radio waves) 85 1.0 coax. cable (75% velocity) 113 1.8 coax. cable (66% velocity) 129 2.3 fr4 pcb, outer trace 140 - 180 2.8 - 4.5 fr4 pcb, inner trace 180 4.5 alumina pcb, inner trace 240 - 270 8 - 10
6 i n development a graphical summary of table 9 is shown in figure 3. the drawing assumes that the fb input is driven by a clock output programmed with zero skew. depending upon the state of the nf[1:0] pins the respective clocks will be skewed, divided, or inverted relative the fedback output as shown in figure 3. 1.3 output drive, synchronization, and power supplies: the ut7r995 employs flexible output buffers providing the user with selectable drive st rengths, independent power sup- plies, and synchronization to eith er edge of the reference input. using the 3-level pe/hd pin, the user selects the reference edge synchronization and the output dr ive strength for all clock out- puts. the options for edge sy nchronization and output drive strength selected by the pe/hd pin are listed in table 11. when the outputs are configured for low drive operation, they will provide a minimum 12ma of drive current regardless of the selected output power supply. if the outputs are configured for high drive operation, they will provide a minimum 24ma of drive current under a 3.3v power supply and 20ma when pow- ered from a 2.5v supply. notes: 1. please refer to "dc parameters" section for i oh /i ol specifications. the ut7r995 features split po wer supply buses for banks 1 and 2, bank 3, and bank 4. these independent power supplies enable the user to obtain both 3.3v and 2.5v output signals from one ut7r995 device. the core power supply (v dd ) must run from a 3.3v power supply. table 12 summarizes the power supply operations available with the ut7r995. t 0 t 0 - 6t u t 0 - 5t u t 0 - 3t u t 0 - 1t u t 0 + 1t u t 0 + 2t u t 0 + 3t u t 0 + 4t u t 0 + 5t u t 0 + 6t u t 0 - 4t u t 0 - 2t u xtal1 input fb input -6t u +2t u +3t u +4t u +6t u divided -4t u -3t u -2t u -1t u 0t u +1t u inverted 1f[1:0] 2f[1:0] 3f[1:0] 4f[1:0] (n/a) (n/a) lm lm ll ll lh lh lm lm (n/a) (n/a) lh lh ml ml ml ml (n/a) (n/a) mm mm mm mm mh mh (n/a) (n/a) hl hl mh mh hm hm (n/a) (n/a) hh hh hl hl (n/a) (n/a) hm hm (n/a) (n/a) ll/hh ll (n/a) (n/a) (n/a) hh figure 3. typical outputs with fb connected to a zero-skewed output table 11: pe/hd settings pe/hd synchronization output drive strength 1 l negative low drive m positive high drive h positive low drive
7 i n development notes: 1. please refer to "dc parameters" section for i oh /i ol specifications. 1.4 oscillator characteristics: the ut7r995 accepts a quartz crys tal oscillator, ceramic reso- nator, or 3.3v digital clock. xtal1 and xtal2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in figure 3. to drive the ut7r995 from an external clock source, xtal1 should be driven, while xtal2 floats, as shown in figure 4. 2.0 radiation hardness: the ut7r955 incorporates sp ecial features ensuring its operation in radiation intensive environments. notes: 1. the ut7r995 is immune to la tchup to particles >109 mev-cm 2 /mg. 2. worst case temperature and voltage of t c = +125 o c, v dd = 3.6v, v dd q1/q3/q4 = 3.6v for sel. 3. worst case temperature and voltage of t c = +25 o c, v dd = 3.0v, v dd q1/q3/q4 = 3.0v for seu. 4. adams 90% worst case particle en vironment, geosynchronous orbit, 100mils of aluminum shielding. notes: 1. all seu data specified in this datasheet is based on the storage elements used in the ut7r995. for a detailed white pa per study of single event transient (set) effects on the phase-locked loop (pll), please contact aeroflex colo- rado springs at 719-594-8048. table 12: power supply constraints v dd v dd q1 1, 2 v dd q3 1, 2 v dd q4 1 3.3v 3.3v or 2.5v 3.3v or 2.5v 3.3v or 2.5v c1 c2 xtal2 xtal1 v ss figure 4. oscillator i/f c1, c2 = 30pf + 10pf for crystals. select crystal with 20pf parallel load capacitance. n/c external oscillator signal xtal2 xtal1 v ss figure 5. external clock drive configuration table 13: radiation hardne ss design specifications parameter limit units total ionizing dose (tid) >1e6 rads(si) single event latchup (sel) 1, 2 >109 mev-cm 2 /mg seu saturated cross-section ( sat ) 1.0e-8 cm 2 /device onset single event upset (seu) let threshold 3 109 mev-cm 2 /mg neutron fluence 1.0e14 n/cm 2 dose rate upset tbd rads(si)/sec dose rate survivability tbd rads(si)/sec table 14: weibull and device parameters (256 registers 1 ) parameter limit units shape parameter tbd -- width parameter tbd -- structural cross-section ( )1.0e-8 cm 2 /device onset let 109 mev-cm 2 /mg depletion depth tbd m funnel depth tbd m
8 i n development 3.0 pin description flatpack pin no. cga pin no. name i/o type description 37 a4 xtal1 i lvttl crystal or single ended reference input. if used with a crystal, the second pin on the crystal must be conn ected to xtal2. if a singled ended reference clock is supplied to this pin, then xtal2 should be left unconnected. 36 e4 xtal2 o lvttl feedback output from the on -board crystal oscillator. when a crystal is used to supply the reference frequency for the ut7r995, this pin must be connected to the second terminal of the crystal resonator. if a single- ended reference clock is supplied to xt al1, then this output should be left unconnected. 13 d4 fb i lvttl feedback input for the pll. 28 g6 test 1 i 3-level built-in test control signal. when test is set to the mid or high level, it disables the pll and the xtal1 re ference frequency is driven to all outputs (except for the conditions described in note 2). set test low for normal operation. 3b4soe i lvttl synchronous output enable. the soe input is used to synchronously enable/disable the output cl ocks. each clock output that is controlled by the soe pin is synchronously enabled/disabled by the individual output clock. when high , soe disables all clocks except 2q0 and 2q1. when disabled, 1q0, 1q1, 3q0, and 3q1 will always enter a low state when pe/hd is mid or high , and they will disable into a high state when pe/hd is low . the disabled state of 4q0 and 4q1 is dependant upon the state of pe/ hd and 4f[1:0]. the following table i llustrates the disabled state of bank 4 outputs as they are controlled by the state of pe/hd and 4f[1:0]. pe/hd 4f[1:0]* 4q0 4q1 low hh low low mid hh high high high hh high high *all other combinations of 4f[1:0] will result in 4q0 and 4q1 disabling into a low state when pe/hd is mid or high , and they will disable into a high state when pe/hd is low . when test is held at the mid level and soe is high , the nf[1:0] pins act as individual output enable/disab le controls for each output bank, excluding bank 2. setting both nf[1:0] signals low disables the corresponding output bank. set soe low to place the ut7r995 radclock tm outputs into their normal operating modes. 1, 2, 24, 25, 26, 27, 47, 48 a3, a5, b3, b5, f3, f5, g3, g5 nf[1:0] i 3-level output divider and phase skew se lection for each output bank. please see tables 3, 4, 5, 6, and 9 for a complete explanation of the nf[1:0] control functions and their ef fects on output frequency and skew. 46 a6 fs i 3-level vco operating frequency range selection. please see tables 7 and 8.
9 i n development 8, 9, 17, 18, 31, 32, 41, 42 c1, c2, c6, c7, e1, e2, e6, e7 nq[1:0] o lvttl four clock banks of two outputs each. please see table 6 for frequency settings and table 9 for skew settings. 22, 23 g2, g4 ds[1:0] i 3-level feedback input di vider selection. please see table 1 for a summary of the feedback input divider settings. 5 a2 pe/hd i 3-level positive/negative edge control and high/low output drive strength selection. the pe portion of this pin controls which edge of the reference input synchronizes the clock outputs. the hd portion of this pin controls the drive strength of the output clock buffers. the following table summarizes the effects of the pe/ hd pin during normal operation. pe/hd synchronization output drive strength low negative edge low drive mid positive edge high drive high positive edge low drive low drive strength outputs provide 12ma of drive strength while the high drive condition results in 24ma of current drive. output banks operating from a 2.5v power supply guarantee a high drive of 20ma. 4a4pd /div i 3-level power down and reference divider control. this dual function pin controls the power down operation and selects the input reference divider. the following table summari zes the operating states controlled by the pd /div pin. pd /div operating mode input reference divider low powered down n/a mid normal operation 2 high normal operation 1 20 f4 lock o lvttl pll lock indication signal. a high state indicates that the pll is in a locked condition. a low state indicates that the pll is not locked and the outputs may not be synchronized to the input. 43 c5 v dd q4 2 pwr power power supply for bank 4 output buffers. please see table 12 for supply level constraints. 7c3 v dd q3 2 pwr power power supply for bank 3output buffers. please see table 12 for supply level constraints. 19, 30 e3, e5 v dd q1 2 pwr power power supply for bank 1 and bank 2 output buffers. please see table 12 for supply level constraints. 6, 12, 14, 35, 38 b3, b6, d1, d5, d7, f2, f6 v dd 2 pwr power power supply for internal circuitry. please see table 12 for supply level constraints. 10, 11, 15, 16, 21, 29, 33, 34, 39, 40, 44, 45 a1, a7, b1, b7, d2, d3, d6, f1, f7, g1, g7 v ss pwr power ground flatpack pin no. cga pin no. name i/o type description notes: 1. when test = mid and soe = high, the pll remains active with nf[1:0] = ll functioning as an output disable cont rol for individual output banks. skew se lections remain in effect unless nf[1:0] = ll. 2. a bypass capacitor (0.1 f) should be placed as close as possible to each positive power pin (<0.2"). an additional 1 f capacitor should be located within 0.2" of the output bank power supplies (v dd q1, v dd q3, and v dd q4). if these bypass capacitors are not close to the pi ns, their high frequency filtering characteristics will be cancelled by the lead inductance of the traces.
10 i n development 4.0 absolute maximum ratings: 1 (referenced to v ss ) notes: 1. stresses outside the listed absolute maximum ratings may caus e permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. maximum junction temperat ure may be increased to +175 c during burn-in and steady-static life. 5.0 recommended operating conditions: symbol description limits units v dd core power supply vo ltage -0.3 to 4.0 v v dd q1, v dd q3, and v dd q4 output bank power supply voltage -0.3 to 4.0 v v in voltage any input pin -0.3 to v dd + 0.3 v v out voltage any clock bank output -0.3 to v dd qn + 0.3 v v o voltage on xtal2 and lock outputs -0.3 to v dd + 0.3 v i i dc input current + 10 ma p d maximum power dissipation 1 w t stg storage temperature -65 to +150 c t j maximum junction temperature 2 +150 c jc thermal resistance, junction to case 15 c/w esd hbm esd protection (human body model) - class ii 3500 v symbol description limits units v dd core operating voltage 3.0 to 3.6 v v dd q1, v dd q3, and v dd q4 output bank operating voltage 2.25 to 3.6 v v in voltage any configuration and control input 0 to v dd v v out voltage any bank output 0 to v dd qn v t c case operating temperature -55 to +125 c
11 i n development 6.0 dc input electrical characteristics (pre- and post-radiation)* (v dd = +3.3v + 0.3v; t c = -55 c to +125 c) notes: * post-radiation perform ance guaranteed at 25 c per mil-std-883 method 1019, condition a up to a tid level of 1.0e6 rad(si). 1. functional tests are conducted in accordance with mil-std-883 with the followi ng input test conditions: v ih = v ih(min) +20%, -0%; v il = v il(max) +0%, -50%, as specified herein for lvttl and lvcmos inputs. for 3-level inputs, v ih = v ihh(min) +50%, -0%; v il = v ill(max) +0%, -50%; v im = v imm(nom) +0.1v, -0.1v. devices may be tested using any input voltage within the above specified range, but are guaranteed to v ih(min) , v il(max) , v ihh(min) , v ill(max) , and v imm(nom) . 2. these inputs are no rmally wired to v dd , v ss , or left unconnected. intern al termination resistors bias unconnected inputs to v dd /2 + 0.3v. the 3-level inputs include: test, pd /div, pe/hd, fs, nf[1:0], ds[1:0]. 3. capacitance is measured for initial qualification and when de sign changes may affect the in put/output capacitance. capacitan ce is measured between the designated terminal and v ss at frequency of 1mhz and a sign al amplitude of 50mv rms maximum. symbol description conditions min. max. units v ih 1 high-level input voltage (xtal1, fb and soe inputs) 2.0 -- v v il 1 low-level input voltage (xtal1, fb and soe inputs) -- 0.8 v v ihh 1,2 high-level input voltage v dd - 0.6 -- v v imm 1,2 mid-level input voltage v dd 2 - 0.3 v dd 2 + 0.3 v v ill 1,2 low-level input voltage -- 0.6 v i il input leakage current (xtal1 and fb inputs) v in = v dd or v ss; v dd = max -5 5 a i 3l 2 3-level input dc current high, v in = v dd -- 200 a mid, v in = v dd /2 -50 50 a low, v in = v ss -200 -- a i ddq quiescent supply current v dd = max; v dd qn = +2.75v; test = mid; xtal1 & soe = low; outputs not loaded -- 2 ma i ddpd power-down current pd /div & soe = low; test, nf[1:0], & ds[1:0] = high v dd = max; v dd qn = +2.75v 10 (typ) 25 a c in-2l 3 input pin capacitance 2-level inputs f = 1mhz @ 0v; v dd = max 8.5 pf c in-3l 3 input pin capacitance 3-level inputs f = 1mhz @ 0v; v dd = max 15 pf
12 i n development 7.0 dc output electrical characteristics (pre- and post-radiation)* (v dd qn = +2.5v + 10%; v dd = +3.3v + 0.3v; t c = -55 c to +125 c) (v dd qn = +3.3v + 0.3v; v dd = +3.3v + 0.3v; t c = -55 c to +125 c) notes: * post-radiation performance guaranteed at 25 c per mil-std-883 method 1019, condition a up to a tid level of 1.0e6 rad(si). 1. supplied as a design limit. neither guaranteed nor tested. 2. capacitance is measured for initial qualification and wh en design changes may affect the input/output capacitance. capacitan ce is measured between the designated terminal and v ss at frequency of 1mhz and a signa l amplitude of 50mv rms maximum. symbol description conditions min. max. units v ol output low voltage i ol = 12ma (pe/hd = low or high); (pins: nq[1:0]) -- 0.4 v i ol = 20ma (pe/hd = mid); (pins: nq[1:0]) -- 0.4 v i ol = 2ma (pins: lock) -- 0.4 v v oh high-level output voltage i oh = -12ma (pe/hd = low or high); (pins: nq[1:0]) 2.0 -- v i oh = -18ma (pe/hd = mid); (pins: nq[1:0]; v dd qn = +2.25v) 2.0 -- v i oh = -20ma (pe/hd = mid); (pins: nq[1:0]; v dd qn = +2.375v) 2.0 -- v i oh = -2ma (pins: lock) 2.4 -- v i os qn 1 short-circuit output current v o = v dd qn or v ss ; v dd qn = +2.75v; pe/hd = mid -500 500 ma v o = v dd qn or v ss ; v dd qn = +2.75v; pe/hd = low or high -300 300 ma i ddop dynamic supply current @200mhz; v dd = max; v dd qn = +2.75v; c l = 20pf/output -- 250 ma @100mhz; v dd = max; v dd qn = +2.75v; c l = 20pf/output -- 150 ma @50mhz; v dd = max; v dd qn = +2.75v; c l = 20pf/output -- 100 ma c out 2 output pin capacitance f = 1mhz @ 0v; v dd = max; v dd qn = +2.75v 15 pf symbol description conditions min. max. units v ol output low voltage i ol = 12ma (pe/hd = low or high); (pins: nq[1:0]) -- 0.4 v i ol = 24ma (pe/hd = mid); (pins: nq[1:0]) -- 0.4 v i ol = 2ma (pins: lock) -- 0.4 v v oh high-level output voltage i oh = -12ma (pe/hd = low or high); (pins: nq[1:0]) 2.4 -- v i oh = -24ma (pe/hd = mid); (pins: nq[1:0]) 2.4 -- v i oh = -2ma (pins: lock) 2.4 -- v i os qn 1 short-circuit output current v o = v dd qn or v ss ; v dd qn = +3.6v; pe/hd = mid -600 600 ma v o = v dd qn or v ss ; v dd qn = +3.6v; pe/hd = low or high -300 300 ma i ddop dynamic supply current @200mhz; v dd = max; v dd qn = +3.6v; c l = 20pf/output -- 400 ma @100mhz; v dd = max; v dd qn = +3.6v; c l = 20pf/output -- 230 ma @50mhz; v dd = max; v dd qn = +3.6v; c l = 20pf/output -- 150 ma c out 2 output pin capacitance f = 1mhz @ 0v; v dd = max; v dd qn = +3.6v 15 pf
13 i n development 8.0 ac input electrical characteristics (pre- and post-radiation)* (v dd = +3.3v + 0.3v; t c = -55 c to +125 c) notes: * post-radiation perform ance guaranteed at 25 c per mil-std-883 method 1019. 1. tested on initial qualification and af ter any design or process changes that may affect this characteristic. 2. although the input reference frequencies are defined as-low-as 2mhz, the n and r dividers must be selected to ensure the pll operates from 24mhz-50mhz when fs = low, 48mhz-100mhz when fs = mi d, and 96mhz-200mhz when fs = high. symbol description condition min. max. unit t r , t f 1 input rise/fall time vih(min)-vil(max) -- 10 ns/v t pwc input clock pulse high or low 2 -- ns t xtal input clock period 1 f xtal 5500ns t dcin input clock duty cycle high or low 10 90 % f xtal 2 reference input frequency fs = low; pd /div = high 2 50 mhz fs = low; pd/div = mid 4 100 mhz fs = mid; pd /div = high 4 100 mhz fs = mid; pd /div = mid 8 200 mhz fs = high; pd /div = high 8 200 mhz fs = high; pd /div = mid 16 200 mhz
14 i n development 9.0 ac output electrical characteris tics (pre- and post-radiation)* (v dd = +3.3v + 0.3v; t c = -55 c to +125 c) notes: 1. supplied as a design limit. neither guaranteed nor tested. 2. test load = 40pf, terminated to v dd 2. all outputs are equally loaded. see figure 11. 3. t pd is measured at 1.5v for v dd = 3.3v with xtal1 rise/fall times of 1ns between 0.8v-2.0v. 4. t lock is the time that is required before outputs synchronize to xtal1. this specification is valid with stable power supplies which are within normal operating limits. 5. lock detector circuit may be unreliable for input frequencies lower than 4mhz, or for input si gnals which contain more than tbd ps or tbd% of jitter. symbol description condition min. max. unit f or output frequency range 6 200 mhz vco lr vco lock range 24 200 mhz vco lbw 1 vco loop bandwidth 0.25 3.5 mhz t skewpr 2 matched-pair skew skew between the earliest and the latest output transitions within the same bank. -- 100 ps t skew0 2 output-output skew skew between the earliest and the latest output transitions among all outputs at 0t u . -- 200 ps t skew1 2 skew between the earliest and the latest output transitions among all outputs for which the same phase delay has been selected. -- 200 ps t skew2 2 skew between the nomina l output rising edge to the inverted output falling edge -- 500 ps t skew3 2 skew between non-inve rted outputs running at different frequencies. -- 500 ps t skew4 2 skew between nominal to inverted outputs running at different frequencies. -- 500 ps t skew5 2 skew between nominal outputs at different power supply levels. -- 650 ps t pa rt part-part skew skew between the outputs of any two devices under identical settings and conditions (v dd qn, v dd , temp, air flow, frequency, etc). -- 750 ps t pd0 3 xtal1 to fb propagation delay -250 +250 ps t odcv output duty cycle fout < 100 mhz, measured at v dd 2 48 52 % fout > 100 mhz, measured at v dd 2 45 55 % t pwh output high time deviation from 50% measured at 2.0v -- 1.5 ns t pwl output low time deviation from 50% measured at 0.8v -- 2.0 ns t r /t f output rise/fall time measured as transition time between v oh(min) and v ol(max) for v dd qn = 2.25v and 2.75v; c l = 40pf 0.15 1.5 ns measured as transition time between v oh(min) and v ol(max) for v dd qn = 3.0v and 3.6v; c l = 40pf 0.10 1.5 ns t lock 4,5 pll lock time -- 500 ms t ccj cycle-cycle jitter divide by 1 output frequency, fs = low, fb = divide by any -- 100 ps divide by 1 output frequency fs = mid or high, fb = divide by any -- 150 ps
15 i n development xtal1 fb nq0 nq1 inverted q xtal1 2 xtal1 4 t xtal t pwc t pd0 t odcv t dcin t odcv t ccj(1-12) t skewpr t skew0, t skew1 t skew2 t skew4 t skew3 t skew5 (v dd qn = 2.5v) (v dd qn = 3.3v) figure 6. ac timing diagram
16 i n development figure 10. lock output test load circuit 2.0v 0.8v v th = 1.5v t pwh t pwl t orise t ofall figure 7. +3.3v lvttl output waveform 1.7v 0.7v v th = 1.25v t pwh t pwl t orise t ofall figure 8. +2.5v lvttl output waveform 2.0v 0.8v v th = 1.5v < 1ns < 1ns figure 9. +3.3v lvttl input test waveform 3.0v 0v c l 150 ? 150 ? v dd qn d ut figure 11. clock output ac test load circuit 100 ? 100 ? c l dut
17 i n development figure 12. 49-pin ceramic colu mn grid array (9mm x 9mm)
18 i n development figure 13. 48-lead ceramic flatpack 1. all exposed metallized areas are gold plated over electroplated nickel per mil-prf-38535. 2. the lid is electrically connected to v ss . 3. lead finishes are in accordance with mil-prf-38535. 4. lead position and cola narity are not measured. 5. id mark symbol is vendor option. 6. with solder, increase maximum by 0.003. 6 4 5 6
19 i n development ordering information ut7r995: lead finish (notes 1 & 2): (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) screening (notes 3 & 4): (c) = military temperature range flow (-55 c to +125 c) (p) = prototype flow package type: (x) = 48-lead ceramic flatpack (y) = 49-pin ceramic colu mn grid array (pending) notes: 1. lead finish (a,c, or x) must be specified. 2. if an ?x? is specified when ordering, then the part marking will match the lead finish and will be either ?a? (solder) or ?c? (gold). 3. prototype flow per utmc manufactur ing flows document. tested at 25 c only. lead finish is gold only. ra diation neither tested nor guaranteed. 4. military temperature range flow per aero flex colorado springs manufacturing flow s document. devices are tested at -55 c, room temp, and 125 c. radiation neither tested nor guaranteed. ut7r995 - * * *
20 i n development ut7r995: smd lead finish (notes 1 & 2): (a) = hot solder dipped (c) = gold (x) = factory option (gold or solder) case outline: (x) = 48-lead ceramic flatpack (y) = 49-pin ceramic colu mn grid array (pending) class designator: (q) = qml class q (v) = qml class v device type (01) = 6mhz-to-200mhz, high speed, multi-p hase, zero-delay, clock generator drawing number: 5962-05214 total dose (note 3): (r = 1e5 rads(si) (f) = 3e5 rads(si) (g) = 5e5 rads(si) (h) = 1e6 rads(si) federal stock class designator: no options notes: 1.lead finish (a,c, or x) must be specified. 2.if an ?x? is specified when ordering, part marking will match the lead finish and will be eith er ?a? (solder) or ?c? (gold). 3.total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening. 5962 * 05214 ** * * *
21 colorado toll free: 800-645-8862 fax: 719-594-8468 se and mid-atlantic tel: 321-951-4164 fax: 321-951-4254 international tel: 805-778-9229 fax: 805-778-1980 west coast tel: 949-362-2260 fax: 949-362-2266 northeast tel: 603-888-3975 fax: 603-888-4585 central tel: 719-594-8017 fax: 719-594-8468 www.aeroflex.com info-ams@aeroflex.com our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused aeroflex colorado springs, inc., reserves the right to make changes to any products and services herein at any time without notice. consult aeroflex or an authorized sales representative to verify that the information in this data sheet is current before using this product. aeroflex does not assume any responsibility or liability arising out of the application or use of any product or service described herein, except as expressly agreed to in writing by aeroflex; nor does the purchase, lease, or use of a pr oduct or service from aeroflex convey a license under any patent rights, copyrights, trademark rights, or any other of the intellectual rights of aeroflex or of third parties.

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